Description
FC1001_RMII contains all functions to add a FPGA to an Ethernet network with a Reduced Media Independent Interface, RMII.
This is the smallest core with only the absolute necessary functions to enable UDP communication.
The UDP interface is a standard AXI Stream interface with status signals.
The core is available for Xilinx 7 Series.
Signal Interface
| Name | Direction | Width | Remarks |
|---|---|---|---|
| Sys/Common | |||
| Clk | in | 1 | 100 MHz |
| Reset | in | 1 | Active high |
| UseDHCP | in | 1 | '1' to use DHCP |
| IP_Addr | in | 32 | IP address if not using DHCP |
| IP_Ok | out | 1 | DHCP ready |
| MAC/RMII | |||
| RMII_CLK_50M | out | 1 | RMII continous 50 MHz reference clock |
| RMII_RST_N | out | 1 | Phy reset, active low |
| RMII_CRS_DV | in | 1 | Carrier sense/Receive data valid |
| RMII_RXD0 | in | 1 | Receive data bit 0 |
| RMII_RXD1 | in | 1 | Receive data bit 1 |
| RMII_RXERR | in | 1 | Receive error, optional |
| RMII_TXEN | out | 1 | Transmit enable |
| RMII_TXD0 | out | 1 | Transmit data bit 0 |
| RMII_TXD1 | out | 1 | Transmit data bit 1 |
| RMII_MDC | out | 1 | Management clock |
| RMII_MDIO | in/out | 1 | Management data |
| UDP Basic Server | |||
| UDP0_Reset | in | 1 | Reset interface, active high |
| UDP0_Service | in | 16 | Service |
| UDP0_ServerPort | in | 16 | UDP local server port |
| UDP0_Connected | out | 1 | Client connected |
| UDP0_OutIsEmpty | out | 1 | All outgoing data acked |
| UDP0_TxData | in | 8 | Transmit data |
| UDP0_TxValid | in | 1 | Transmit data valid |
| UDP0_TxReady | out | 1 | Transmit data ready |
| UDP0_TxLast | in | 1 | Transmit data last |
| UDP0_RxData | out | 8 | Receive data |
| UDP0_RxValid | out | 1 | Receive data valid |
| UDP0_RxReady | in | 1 | Receive data ready |
| UDP0_RxLast | out | 1 | Transmit data last |
Downloads
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The HDL code and netlists are distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
VHDL Component: FC1001_RMII.vhd
Verilog Module: FC1001_RMII.vh
Xilinx 7 Series Netlist: FC1001_RMII.edn
Xilinx Spartan 6 Netlist: FC1001_RMII.ngc