Description
FC1003_RMII contains functions for remote flash programming, UDP communication and a logic analyzer for debugging. All this in a single easy to use core.
The UDP interface is a standard AXI Stream interface with status signals.
Flash programming is done with FPGA Programmer.
The core is available for Xilinx 7 Series.
Signal Interface
| Name | Direction | Width | Remarks |
|---|---|---|---|
| Sys/Common | |||
| Clk | in | 1 | 100 MHz |
| Reset | in | 1 | Active high |
| UseDHCP | in | 1 | '1' to use DHCP |
| IP_Addr | in | 32 | IP address if not using DHCP |
| IP_Ok | out | 1 | DHCP ready |
| MAC/RMII | |||
| RMII_CLK_50M | out | 1 | RMII continous 50 MHz reference clock |
| RMII_RST_N | out | 1 | Phy reset, active low |
| RMII_CRS_DV | in | 1 | Carrier sense/Receive data valid |
| RMII_RXD0 | in | 1 | Receive data bit 0 |
| RMII_RXD1 | in | 1 | Receive data bit 1 |
| RMII_RXERR | in | 1 | Receive error, optional |
| RMII_TXEN | out | 1 | Transmit enable |
| RMII_TXD0 | out | 1 | Transmit data bit 0 |
| RMII_TXD1 | out | 1 | Transmit data bit 1 |
| RMII_MDC | out | 1 | Management clock |
| RMII_MDIO | in/out | 1 | Management data |
| SPI/Boot Control | |||
| SPI_CSn | out | 1 | Chip select |
| SPI_SCK | out | 1 | Serial clock |
| SPI_MOSI | out | 1 | Master out slave in |
| SPI_MISO | in | 1 | Master in slave out |
| Logic Analyzer | |||
| LA0_TrigIn | in | 1 | Trigger input |
| LA0_Clk | in | 1 | Clock |
| LA0_TrigOut | out | 1 | Trigger out |
| LA0_Signals | in | 32 | Signals |
| LA0_SampleEn | in | 1 | Sample enable |
| UDP Basic Server | |||
| UDP0_Reset | in | 1 | Reset interface, active high |
| UDP0_Service | in | 16 | Service |
| UDP0_ServerPort | in | 16 | UDP local server port |
| UDP0_Connected | out | 1 | Client connected |
| UDP0_OutIsEmpty | out | 1 | All outgoing data acked |
| UDP0_TxData | in | 8 | Transmit data |
| UDP0_TxValid | in | 1 | Transmit data valid |
| UDP0_TxReady | out | 1 | Transmit data ready |
| UDP0_TxLast | in | 1 | Transmit data last |
| UDP0_RxData | out | 8 | Receive data |
| UDP0_RxValid | out | 1 | Receive data valid |
| UDP0_RxReady | in | 1 | Receive data ready |
| UDP0_RxLast | out | 1 | Transmit data last |
Downloads
Copyright ©2018 FPGA-Cores.com.This HDL code and netlists are only free to use for non - commercial users and for evaluation purpose. Commercial use needs a commercial license.
The HDL code and netlists are distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
VHDL Component: FC1003_RMII.vhd
Verilog Module: FC1003_RMII.vh
Xilinx 7 Series Netlist: FC1003_RMII.edn
Xilinx Spartan 6 Netlist: FC1003_RMII.ngc